The MicroTCA is a computer platform specifications formulated by the PCI Industrial Computers Manufacturers Group (PICMG). The MicroTCA uses standard Advanced Mezzanine Card (AMC) module to construct modularized communication platforms of low capacity and low cost, and is primarily applied to small telecom equipment of a central office or enterprise-class communication equipment. Currently, the latest version of the standard is PICMG MicroTCA.0 R1.0.
FIG. 1 shows a MicroTCA carrier structure in the conventional art. In a MicroTCA carrier, a carrier is composed of a frame, Power Module (PM), MicroTCA switching control module (such as MicroTCA Carrier Hub, MCH), and AMC. Several carriers and a Cooling Unit (CU) constitute a shelf. The MicroTCA in the conventional art is applicable to a cabinet which is 300 mm in depth, or placed in a cabinet 600 mm deep in the back-to-back mode.
FIG. 2 shows a structure of an MCH in the conventional art. The MCH is a switching control module of the MicroTCA carrier, and is the central node of the whole system. The MCH includes a MicroTCA Carrier Management Controller (MCMC) unit, data switching unit, clock unit, and Joint Test Action Group (JTAG) unit. The MCMC unit is a management module of the whole system, and primarily manages the AMC and PM. The IPMB-L is the connection for the MCH to manage the AMC, and the IPMB-0 is the connection for the MCH to manage the PM. The data switching unit is divided into seven switching interfaces which range from Fabric A to Fabric G, and provides data switching of at most 12 AMC cards. The clock unit implements the clock function of the system, including selecting a clock source, generating a system synchronization clock, and driving the generated system clock to each connected AMC card. The CLKx is configured to identify the clock type, and the JTAG unit is configured to perform the test function of the system.
The MicroTCA.0 R1.0 standard defines the maximum height of the MCH to be 6 HP (about 3 cm), which may be implemented through at most 4 Printed Circuit Boards (PCBs). That is, one MCH is composed of 4 PCBs, and the 4 PCBs of the MCH are limited to a 6-HP height. The first PCB enables the MCMC to manage the MicroTCA carrier, and provides the basic switching functions (Fabric A port). The second PCB is configured to implement the Fabric B port for system clock and data switching; the third and fourth PCBs provide Fabric C-to-Fabric G ports (namely, Fat Pipe) of Fabric switching on the data plane. Meanwhile, as defined in the standard, the connector between the MCH and the backplane is composed of 4 tongues, where tongue 1 provides a connection pin between the MCMC unit and JTAG unit, tongue 2 provides a connection pin of the clock unit, and tongue 3 and tongue 4 provide connection pins of the Fat Pipe (namely, ports from Fabric C to Fabric G).
FIG. 3 shows redundancy clock architecture of a MicroTCA carrier in the conventional art. In the MicroTCA.0 R1.0 standard in the conventional art, the MCH implements the clock functions. The MicroTCA system adopts a star clock topology. In the backplane, it is defined that an MCH slot is located at the central node of the star topology, and only the MCH can provide enough pins for connecting with other AMCs. Therefore, the clock module needs to be implemented on the MCH.
FIG. 4 shows implementation of a clock in a MicroTCA carrier in the conventional art. Like the traditional ATCA clock implementation solution, this implementation solution sets a clock module on the central node (namely, MCH) of the system. One clock module includes a clock source selecting unit, phase-lock unit, and clock drive unit. The clock source selecting unit is configured to select a clock source. The clock source refers to any clock source input to the clock module, for example, Global Positioning System (GPS) clock source, Building Integrated Timing Supply System (BITS) clock source, cascaded clock source from the upper stratum, or line clock source from the AMC. The phase-lock unit is configured to perform phase-lock synchronization for the selected clock source, and then obtain a system synchronization clock. The drive unit is configured to input the system synchronization clock into the connected AMC.
In a specific example, typically the MCH provides three types of clocks for the MicroTCA carrier. Clock 2 (CLK2) is one of the optional clock sources provided by each AMC for the clock module in the MCH. Clock 1 (CLK1) and clock 3 (CLK3) are active and standby system synchronization clocks provided by the clock module in the MCH for each AMC.
The clock sources input to the MCH include GPS clock, BITS clock, cascaded input clock, and AMC line clock. Universal input modes are as follows: GPS clock, cascaded input clock, and BITS clock are input through the interface provided by the panel, and the clock sources provided by each AMC are input through the backplane. Interlocking exists between the clock modules located on the active and standby MCHs. After phase-lock synchronization, the MCH outputs the system synchronization clock to each AMC.
FIG. 5 shows an AMC port configuration table in the conventional art. This configuration table is defined by the SCOPE organization, which defines the port assignment of the AMC in detail. This assignment scheme will be an important basis for port assignment in the next version of the AMC standard and MicroTCA standard. That is, the AMC port assignment shown in FIG. 5 will apply in formulating the AMC-related standards. The AMC may provide 4 communication clock channels, including two input clock ports (TCLKA, TCLKC), which receive the system synchronization clock from the active and standby MCHs, and two output clock ports (TCLKB, TCLKD), which provide line clock sources for the MCH. The AMC also provides 21 data ports: 4 public area ports (port 0-3), 8 Fat Pipe switching ports (Ports 4-11), and 9 extended area ports, where port 12 is configured to provide a data update channel through direct interconnection between AMCs.
FIG. 6 shows assignment of multi-frame cascaded clocks in a MicroTCA carrier in the conventional art. In the case of multi-frame cascading in the MicroTCA carrier, a clock module is set on the MCH of each carrier. FIG. 4 shows details of the clock module. In the case of multi-frame cascading, clock modules are also set on the MCH of the slave frame, and each such clock module is consistent with the clock module in the MCH of the master frame and also includes a clock source selecting unit, phase-lock and crystal oscillation unit, and drive unit, etc. In this case, the drive unit of the active MCH in the master frame outputs the system synchronization clock to the active MCH in each slave frame through cascaded connection. By analogy, the standby MCH in the master frame provides the system synchronization clock for the standby MCH in each slave frame.
In the process of implementing the present invention, the inventor finds that, in the conventional art, the clock system in practice involves the following defects because the clock module in the MicroTCA is implemented on the MCH, the MCH is limited to physical specifications, and switching, management and clock functions need to be implemented concurrently:
First, the MicroTCA standard defines the physical specifications of the MCH. Due to limitation of the physical space, the clock implementation is difficult. For example, if the required clock precision is enhanced stratum 3, the clock board requires the height of the constant-temperature crystal oscillator to be more than 1 cm, and at least two PCBs need to be deployed on the MCH. In order to implement clocks of enhanced stratum 3 or higher stratum, the physical size of the MCH specified in the standard is hardly accomplishable.
Moreover, in the case of multi-frame cascading, the configuration of the clock module in the slave frame is consistent with the configuration of the clock module in the master frame. In practice, however, some units (such as phase-lock unit) in the clock module of the slave frame may be left idle. Therefore, such configuration in the conventional art increases the system cost.